Manage ASIC and SoC design risk with industry-leading verification services

What you will learn:

  • Value in design prototyping using FPGAs.
  • Design validation with firmware.
  • How the process works.
  • Identifying companies with the right experience and expertise in FPGAs and design prototyping capabilities can help avoid costly respins.

The Performance Benefits of ASICs and Advanced SoCs (Fig.1) are well known to the companies that develop them and to their customers. Thus, the design challenges and risks that come with complex product design (bugs, defects, and failures that can require costly responses) are worth considering.

Managing these risks is key to reducing or eliminating production delays and associated costs. One task throughout the design timeline where risk can be reduced is prototyping and verification.

The value of FPGA in prototyping

FPGAs are useful for prototyping ASICs and SoCs, and have been proven to reduce risk of delays and speed products to market when used pre- and post-tape release. The components needed to work with a system on a chip (SoC) are connected and tested with an FPGA prototype on a hardware platform. Chip design and firmware are reprogrammed until the SoC design is final and bug-free before manufacturing of a final SoC begins.

Performance issues found in connected components of the SoC on the FPGA hardware platform are addressed by modifying component selection, performance testing, and other actions so that performance can be verified before the chip returns from the foundry.

Chip verification is an essential part of the design cycle and should run in parallel. Verification can ensure that all parts or features of the chip are working properly.

Conventional verification techniques such as RTL (register transfer level) simulations, gate-level simulations, system-level simulation, BIST (built-in self-test), DFT (design for testability) verification and others are useful, but they are generally not enough to ensure the success of an SoC.

Design validation with firmware

Conventional RTL simulation can take days or weeks. For example, moving a video input frame through various pipelines and analyzing the data in the SoC before the processed video or data is passed to external I/O. Speeding up this type of simulation is essential for successful SoC verification.

Actual functional testing must be performed on an actual hardware platform. Examples include testing a camera that transmits video to an external host PC via PCIe or USB, or displaying video on a display device, or sending data to another device using a real serial link.

To test that all components connected to the SoC are working properly, firmware and software development is essential for simulations before silicon is available. (Fig.2).

If a problem is discovered during silicon testing, it is essential to know if the problem is in the firmware (FW) or if it is in the silicon. Firmware is used to verify silicon and functions as the base layer for developers to create the software that serves as the backbone for users.

Testing of external hardware components connected to the SoC must also be completed before silicon is available, and this testing must use the physical design. All issues must be resolved prior to tapeout. Monitoring and measuring the performance of the SoC design with real hardware/data should also precede the tapeout. FPGA prototyping of the SoC on a hardware platform provides the vehicle for all of these tests.

How the process works

To develop the firmware, the SoC partner with an experienced FPGA team will implement the design on an FPGA platform for functional testing.

There is a limit to the number of basic features and tests possible while the design is in progress. Therefore, customers and partners should work together throughout the design process using the FPGA prototype to write firmware, test functions, perform engineering change order (ECO), and retest to ensure that the designs are properly made and work well. Firmware is continuously developed as new features and functionality are added.

The Verification Service performs two main tasks simultaneously: using firmware to verify the functionality of the design and ensuring that the firmware is working properly. The same FPGA prototype also allows customers to test other product components with the actual design on an FPGA prototyping hardware platform. Since these activities occur in parallel with the physical design, they help speed up the design process and eventual production time.

FPGA and Socionext Design Capabilities

There are various commercially available prototyping platforms such as HAPS, Protium, S2C, etc. Socionext has established expertise in implementing large SoC designs on these various FPGA prototyping platforms, including using Synopsys HAPS.

It is capable of implementing an entire SoC on the FPGA platform (Fig.3). Some companies have designs that have millions and billions of doors. Socionext has worked with 200, 300 and 500 million door designs.

These many gates cannot be placed on a single FPGA for testing, so the company has implemented designs on boards with multiple FPGAs, with each board having up to four FPGAs with the ability to stack boards . Sometimes four, five, and 10 FPGA boards are stacked to put the entire design on the board to perform firmware testing.

Besides implementing the design on multiple FPGAs, the design can be partitioned to accommodate different FPGAs. An FPGA runs much slower than an ASIC, at around 1 to 10, 50, 100 slower speeds. However, the speed is sufficient to perform tasks such as taking video and capturing network data, sending it to a processing interface to make some intermediate decisions passed to the next chip, or patch.

SoCs are typically large and complex with different types of interfaces that need to be built and tested during this design phase (Fig.4). Mobile device interfaces may include Ethernet, SD card, MIPI, HDMI, and others, and these connectors should be available on the FPGA platform for test verification. Since they don’t all come from a single prototype platform, Socionext has developed platform-compatible daughterboards for most standard interfaces and built custom boards that plug into these platforms, including daughterboards serving as interfaces.

Simultaneous firmware development on an FPGA platform such as HAPS, used by Socionext and many others, provides the same data format to the customer. This means that customer FPGA boards can load the same data design database and then run the test on their end.

Such collaboration allows customers to focus on adding additional layers or software to their designs, while a company like Socionext relies on the initial software layer(s) or two. Customers can also do this by using another partner’s base design with the first layer or firmware provided by Socionext to build software on top of it.

Imitation camera data

Few FPGA boards on the market can operate a camera using the MIPI interface. There is a growing customer demand for this feature, and special designs developed by Socionext solve this problem. Maps mimic camera data (Fig.5) to generate the variance of the test. Customers can pass this data to the Socionext path to test the entire path.

In addition, the daughterboards developed by the company use the MIPI chip and camera (Fig.6) above the daughterboard so that customers can connect the camera using the MIPI chip to a HAPS board. In addition, an internal test mechanism/generator can imitate the camera to run the tests, which can save customers time.

Socionext’s generator and analyzer devices can collect all kinds of data for display and use this data to analyze the display on the video. Both types are available in the laboratory for testing. This helps customers generate multiple datasets and analyzes simultaneously. The single device generator can check many display channels using different types of cameras with the ability to send a wide range of video or image file formats to TV, phone, car and home. other mobile devices.

In addition, a protocol generator and analyzer ensures that each interface conforms to protocols from global standards committees (Fig.7).

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